Aiming to meet the high-efficiency and high-reliability communication requirements of massive spiking neurons in neuromorphic computing chips, in-depth research has been carried out covering key technologies including spiking neuron signal encoding, on-chip network communication architecture, deadlock-free and congestion-aware on-chip network router design, as well as the toolchain for spiking neural network (SNN) mapping optimization.
A field-programmable gate array (FPGA) hardware prototype of neuromorphic on-chip interconnection architecture and a dedicated network mapping optimization toolchain software have been developed. The hardware prototype supports intercommunication among 65,536 neurons and features excellent scalable expansion capability. The effectiveness and feasibility of the hardware prototype have been fully validated on the Synthetic Aperture Radar (SAR) image dataset.
Figure 1. Demonstration of spiking neural network application based on the designed system: ground vehicle type recognition of SAR images. Ten types of vehicles are classified, and the recognition results are indicated by the spike density of output neurons.
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Figure 2. Optimized allocation of spiking neural networks based on the mapping toolchain.
(a) Original neuron connection matrix before optimization; scattered white dots represent nearly random connections of each neuron.
(b) Neuron connection matrix after optimized grouping. The mapping tool extracts neuron connection patterns and reorganizes neurons into different groups with dense intra-group connections and sparse inter-group connections. The grouped clustered mapping effectively reduces on-chip network data traffic, power consumption and transmission latency.
